1. Technical Field of the Invention
The present invention relates to a clock data recovery circuit, more specifically, to a clock data recovery circuit to be used in SONET (Synchronous Optical Network)/SDH (Synchronous Digital Hierarchy) standards for optical communications networks.
2. Description of the Related Art
The American Synchronous Optical Network (SONET) was standardized in the mid 1980s by the American National Standards Institute (ANSI) to efficiently house a third group of circuits (45M bits/second) in optical fiber transmission lines and to form economical digital networks. Furthermore, Synchronous Digital Hierarchy (SDH) is synchronous digital hierarchy specifications standardized as ITU-T (International Telecommunication Union-Telecommunication Standardization Sector) in 1988 based on SONET to unify digital hierarchies different among Japan, the USA, and Europe, and this SDH has realized building of ATM (Asynchronous Transfer Mode) networks on a global level.
Generally, a conventional clock data recovery circuit retimes an input signal by using a clock extracted from the input signal itself, and outputs this retimed signal and the extracted clock. In a clock data recovery circuit used in the SONET/SDH, both an extracted clock that is an output signal from the clock data recovery circuit and output data must have characteristics satisfying the SONET/SDH standards. Particularly, in a digital communications system, excessive jitter causes an unallowable BER (bit error rate), so that a clock extracted from the clock data recovery circuit and output data must have jitter transfer characteristics and jitter tolerance, both of which satisfy the SONET/SDH standards.
FIG. 1 is a block diagram showing a general conventional clock data recovery circuit (Digest of Technical Papers, pp.251, FIG. 15.2.2, 2002 IEEE, International Solid-State Circuits Conference). In the conventional clock data recovery circuit, serial data S401 and a clock S402 outputted from a voltage controlled oscillator (VCO) 407 are inputted into a phase detector (PD) 401 and a frequency detector (FD) 402, respectively, to obtain information on the phase difference and frequency difference between these serial data S401 and clock S402. Obtained phase difference information S403 and frequency difference information S404 are smoothed by a PD filter 403 or an FD filter 404, respectively, to obtain smoothed phase difference information S405 and frequency difference information S406. These smoothed information S405 and S406 are inputted into a weighting circuit 405, weighted, and switched to obtain an output S407. This output S407 from the weighting circuit 405 is inputted into a high-frequency reject filter (low-pass filter: LPF) 406, and an output S408 from this LPF 406 is inputted as input voltage information into the VCO 407. In response to this input voltage, the oscillation frequency of the VCO 407 is controlled and a clock S402 is outputted.
The phase detector 401, the frequency detector 402, the PD filter 403, the FD filter 404, the weighting circuit 405, the LPF 406, and the VCO 407 are connected so as to form a phase-locked loop (PLL). Therefore, the clock S402 outputted from the VCO 407 becomes a clock extracted from the serial data S401. A flip-flop 408 retimes the serial data S401 by the clock S402 outputted from the VCO 407. Therefore, the clock S402 that is extracted for retiming and outputted from the VCO 407 and the retimed serial data S409 outputted from the flip-flop 408 become an output of the clock data recovery circuit.
However, in such a conventional clock data recovery circuit, since this serial data is retimed by the clock extracted from the serial data itself, the phase of the extracted clock and the phase of the clock for retiming cannot be controlled separately. Therefore, in a case where the inputted serial data contains jitter of high-frequency components, standards of both jitter transfer characteristics and jitter tolerance cannot be satisfied.
For example, in the conventional clock data recovery circuit shown in FIG. 1, when the circuit is controlled so as to suppress jitter of the extracted clock S402, jitter transfer characteristics are satisfied. However, if the inputted serial data S401 contains jitter, the flip-flop 408 retimes the data containing jitter by a clock in which jitter has been suppressed, and this causes a data error. Therefore, jitter tolerance is not satisfied. On the other hand, in a case where the circuit is controlled so as not to suppress jitter of the extracted clock S402, even if the inputted serial data S401 contains jitter, the flip-flop 408 retimes the data containing jitter by a clock containing the same jitter, and this reduces the frequency of data errors. Accordingly, jitter tolerance is improved. However, in this case, the extracted clock S402 contains the same jitter as in the inputted serial data S401, so that jitter transfer characteristics cannot be satisfied.